To increase processor performance, clock frequencies used by microprocessors, often referred to as xe2x80x9cCPUsxe2x80x9d, have increased. Also, as the number of circuits that can be used in a CPU has increased, the number of parallel operations has risen. Examples of efforts to create more parallel operations include increased pipeline depth and an increase in the number of functional units in super-scalar and very-long-instruction-word architectures. As processor performance continues to increase, the result has been a larger number of circuits switching at faster rates. Thus, from a design perspective, important considerations, such as switching noise and signal integrity must be taken into account.
As the frequencies of modern computers continue to increase, the need to rapidly transmit data between chip interfaces also increases. To accurately receive data, a clock is often sent to help recover the data. The clock determines when the data should be sampled by a receiver""s circuits.
The clock may transition at the beginning of the time the data is valid. The receiver would prefer, however, to have a signal during the middle of the time the data is valid. Also, the transmission of the clock may degrade as it travels from its transmission point. In both circumstances, a delay locked loop, or DLL, can regenerate a copy of the clock signal at a fixed phase shift from the original.
FIG. 1 shows a section of a typical computer system component (5). Data (8) that is xe2x80x98Nxe2x80x99 bits wide is transmitted from circuit A (6) to circuit B (7). To aid in the recovery of the transmitted data, a clock signal (9) is also transmitted with the data (8). The circuits could also have a path to transmit data from circuit B (7) to circuit A (6) along with an additional clock (not shown). The clock signal (9) may transition from one state to another at the beginning of the data transmission. Circuit B (7) requires a signal temporally located some time after the beginning of the valid data. Furthermore, the clock signal (9) may have degraded during transmission. The DLL has the ability to regenerate the clock signal (9) to a valid state and to create a phase shifted version of the clock to be used by other circuits, for example, a receiver""s sampling signal. The receiver""s sampling signal determines when the input to the receiver should be sampled. The performance of a DLL is critical, and the DLL must maintain a proper reference of time on the CPU, or generically, an integrated circuit.
One common performance measure for a DLL is jitter. Jitter is the time domain error from poor spectral purity of an output. In other words, the clock signal (9) plus a known phase shift, should track the DLL output. For a signal with a repeated pattern, such as a clock, a transition that occurs from one state to another that does not happen at the same time relative to other transitions is said to have jitter. Jitter represents the perturbations that result in the intermittent shortening or lengthening of signal elements. The DLL input, clock signal (9), may have jitter that may need to be transmitted to the DLL output. The DLL, however, may need to filter jitter created by power supply noise.
FIG. 2 shows a block diagram drawing of a representative DLL (200). Clock (201) is input to the representative DLL (200) to create a phased (i.e., delayed) output. Clock (201) is used as an input to a voltage-controlled delay line (210) and to a phase detector (202). The phase detector (202) measures whether the phase difference between clock (201) and an output, clk_out (217), of the delay path is correct. An adjustment in the phase delay produces signals that control a charge pump (204). The phase detector (202) indicates that the charge pump (204) should increase or decrease its output using control signals up, U (203), and down, D (205). Furthermore, internal biasing of the charge pump (204) is dependent on bias signals VBP (209) and VBN (211). The control signals up, U (203), and down, D (205), adjust the current output of the charge pump (204) based on the nominal current set by the control voltages, VBP (209) and VBN (211).
The charge pump (204) adds or removes charge from a capacitor C1 (206), that changes a DC value at the input of a bias-generator (208). The capacitor, C1 (206), is connected between a power supply, VDD, and a control voltage (or control signal), VCTRL (207). The bias-generator (208) produces control voltages (or bias voltages), VBP (209) and VBN (211), in response to the control voltage, VCTRL (207), that control the delay of the voltage-controlled delay line (210).
In FIG. 2, the voltage-controlled delay line (210) may be implemented using current starved elements. This means that the delays are controlled by modifying the amount of current available for charging and discharging capacitances. The linearity of a voltage controlled delay line""s characteristics determines the stable range of frequencies over which the delayed lock loop can operate. Clk_out (217) from the voltage-controlled delay line (210) provides a phase delayed copy of clock (201) to other circuits.
Still referring to FIG. 2, the negative feedback in the loop adjusts the delay through the voltage-controlled delay line by integrating the phase error that results between the periodic reference input, clock (201), and clk_out (217). The voltage-controlled delay line (210) will delay clk_out (217) by a fixed amount of time such that a desired delay between clock (201) and clk_out (217) exists. The speed of the DLL response to a phase error is often related to loop bandwidth.
Delay locked loops are basically first order feedback control systems. As such, the delay locked loop can be described in the frequency domain as having a loop gain and a loop bandwidth. The loop bandwidth is the speed at which a signal completes the feedback loop of the delay locked loop to produce an update (i.e., error signal). Ideally, the DLL should have the highest possible bandwidth so that the clock signal and data track each other. Power supply noise will, however, have a certain noise-versus-frequency characteristic that may require the loop bandwidth to be reduced to attenuate the effects of the power supply noise. The loop bandwidth determines to a large degree what portion of power supply noise is translated to output jitter.
According to one aspect of the present invention, an integrated circuit comprises a clock path for carrying a clock signal; a power supply path adapted to receive power from a power supply; a delay locked loop connected to the power supply path including a phase detector that detects a phase difference between a clock signal and a delayed clock signal, a charge pump, responsive to the phase detector, that outputs a current on a control signal, a bias generator, responsive to the control signal, that generates a bias voltage, and a voltage-controlled delay line, responsive to the bias voltage, that generates the delayed clock signal; and an adjustment circuit operatively connected to the charge pump, where the adjustment circuit is controllable to adjust the current output from the charge pump.
According to one aspect of the present invention, a delay locked loop comprises a phase detector for detecting a phase difference between a clock signal and a delayed clock signal; a charge pump, responsive to the phase detector, that outputs a current on a control signal; a bias-generator, responsive to the control signal, that generates a bias voltage; a voltage-controlled delay line, responsive to the bias voltage, that generates the delayed clock signal; and an adjustment circuit operatively connected to the charge pump, where the adjustment circuit is controllable to adjust the current output from the charge pump.
According to one aspect of the present invention, a method for modifying an operating characteristic of a delay locked loop comprises producing a delayed clock signal; comparing the delayed clock signal to a clock signal; generating a current signal using a charge pump responsive to the comparing; selectively adjusting the current signal using an adjustment circuit operatively connected to the charge pump; and generating a bias voltage to a voltage-controlled delay line dependent on the selectively adjusting, where the voltage-controlled delay line produces the delayed clock signal.
According to one aspect of the present invention, an integrated circuit comprises delay locked loop means for generating a delayed clock signal where the delay locked loop means includes comparing means for detecting a phase difference between a clock signal and the delayed clock signal, charge pumping means for generating a current on a control signal where the charge pumping means is responsive to the comparing means, bias generating means for generating a bias voltage where the bias generating means is responsive to the control signal, and delaying means for generating the delayed clock signal where the delaying means is responsive to the bias voltage; and adjusting means for adjusting the current output from the charge pump where the charge pumping means is responsive to the adjusting means.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.